Attempts have been made for mass scale production of certain types of digital circuitry such as interconnection pads and digital memory by the patterning of thin films of metals and semiconductor on flexible plastic webs in a roll-to-roll production environment. However, plastic web production of such circuitry is currently plagued by deficiencies inherent in the actual patterning methods utilized on flexible substrates. Specifically, existing patterning solutions, such as screen print and ink jet, photolithography, and laser ablation each have deficits in resolution and/or throughput, and can also cause collateral damage. In particular, screen print or inkjet based patterning schemes yield a relatively low throughput, and limited ability to pattern a wide range of materials with uniform standards of resolution. Photolithography, laser ablation, or other optically based patterning methods yield a relatively low throughput, higher capital cost, and low resolution on flexible substrates. This is because the resolution of such optically based schemes is limited by diffraction in proportion to       λ    NA    ,where λ is the wavelength of the illumination and NA is the numerical aperture of the imaging system. Given that the depth of field for the imaging system, and hence its ability to deal with surface irregularities is limited by       λ          NA      2        ,at some point it becomes very difficult to resolve small features on a flexible substrate with such methodologies. This is because it is difficult to clamp a flexible substrate with a vacuum or electrostatic chuck without attracting dust particles to the chuck or substrate surface, or without introducing surface irregularities, especially given the surface roughness typical of flexible webs.
Emboss and liftoff techniques can provide a low cost patterning method for circuitry which has a comparatively high resolution and high throughput when produced on flexible substrates. Despite the advantages of emboss and lift off techniques, several problems do limit its utility for producing electronics which require the large area interconnection pads which offer the advantages of less restrictive tolerance requirements during stacking alignments. In order to use the emboss and lift off process in the manufacture of wide area circuitry such as Permanent Inexpensive, Rugged Memory (PIRM) memory layers, it must be able to provide terminating pads on the end of the electrodes with radii of at least 50 microns. Such terminating pads are required for multi layer interconnect, but the basic emboss and lift off techniques cannot replicate features of this size.
As such, in order to adequately provide for the different types of digital circuitry needed in memory modules, such as the PIRM type memory in certain digital consumer devices, there is a need for the high resolution and throughput of the embossing process when patterning on flexible web sheet substrates without the limitations on producing large area terminating pads.